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mosel vitelic 1 V53C8125H ul tra-high performance, 128k x 8 f ast p a ge mode cmos d ynamic ram preliminar y high performance 30 35 40 45 50 max. ras access time, (t rac ) 30 ns 35 ns 40 ns 45 ns 50 ns max. column address access time, (t caa ) 16 ns 18 ns 20 ns 22 ns 24 ns min. fast page mode cycle time, (t pc ) 19 ns 21 ns 23 ns 25 ns 28 ns min. read/write cycle time, (t rc ) 65 ns 70 ns 75 ns 80 ns 90 ns features n 128k x 8-bit organization n ras access time: 30, 35, 40, 45, 50 ns n fast page mode supports sustained data rates up to 53 mhz n read-modify-write, ras -only refresh, cas -before-ras refresh capability n refresh interval: 256 cycles/8 ms n available in 26/24 pin 300 mil soj and 28 pin tsop-i packages description the V53C8125H is a high speed 131,072 x 8 bit cmos dynamic random access memory. the V53C8125H offers a combination of features: fast page mode for high data bandwidth, fast usable speed, cmos standby current. all inputs and outputs are ttl compatible. input and output capacitances are significantly lowered to allow increased system performance. fast page mode operation allows random access of up to 512 columns (x9) bits within a row with cycle times as short as 19 ns. because of static circuitry, the cas clock is not in the critical timing path. the flow- through column address latches allow address pipelining while relaxing many critical system timing requirements for fast usable speed. these features make the V53C8125H ideally suited for graphics, digital signal processing and high performance pe- ripherals. device usage chart operating temperature range package outline access time (ns) power temperature mark k t 30 35 40 45 50 std. 0 c to 70 c . . . . . . . . blank V53C8125H rev. 1.7 august 1998
2 mosel vitelic V53C8125H V53C8125H re v . 1.7 august 1998 family device pkg (t rac ) speed pwr. v 5 3 c 125 35 (35 ns) 40 (40 ns) 45 (45 ns) 50 (50 ns) temp. blank (0 c to 70 c) blank (normal) k (soj) t (tsop) h 8 8125h 01 pin names a 0 -a 8 address inputs (a 8 : column address only) ras row address strobe cas column address strobe we write enable oe output enable i/o 1 - i/o 8 data input, output v cc +5v supply v ss 0v supply nc no connect description pkg. pin count soj k 26/24 tsop-ii t 28 26/24 lead soj pin configuration top view 28 lead tsop-i pin configuration top view v ss i/o 1 i/o 2 i/o 3 i/o 4 we ras a 0 a 1 a 2 a 3 v cc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 8125h 02 17 16 15 300 mil v ss i/o 8 i/o 7 i/o 6 i/o 5 cas oe a 8 a 7 a 6 a 5 a 4 14 cas i/o5 i/o6 i/o7 i/o8 vss vss nc i/o1 i/o2 i/o3 i/o4 nc we oe a8 a7 a6 a5 a4 nc vcc nc a3 a2 a1 a0 ras 28 27 26 25 24 23 22 21 20 19 18 17 16 15 8125h 03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 30 (30 ns)
mosel vitelic V53C8125H 3 V53C8125H re v . 1.7 august 1998 absolute maximum ratings* ambient temperature under bias ................................. ? 10 c to +80 c storage temperature (plastic) ..... ? 55 c to +125 c voltage relative to v ss ................. ? 1.0 v to +7.0 v data output current ..................................... 50 ma power dissipation .......................................... 1.0 w *note: operation above absolute maximum ratings can ad- versely affect device reliability. capacitance* t a = 25 c, v cc = 5 v 10%, v ss = 0 v *note: capacitance is sampled and not 100% tested. symbol parameter typ. max. unit c in1 address input 3 4 pf c in2 ras , cas , we , oe 45p f c out data input/output 5 7 pf block diagram a 0 a 1 a 7 a 8 sense amplifiers refresh counter v cc v ss 9 8125h 16 i/o 1 address buffers and predecoders row decoders 256 memory array column decoders data i/o bus y 0 ? y 8 x 0 ? x 7 512 x 8 i/o buffer i/o 2 i/o 3 i/o 4 oe clock generator we clock generator cas clock generator ras clock generator oe 128k x 8 we cas ras ? ? ? i/o 5 i/o 6 i/o 7 i/o 8
4 V53C8125H re v . 1.7 august 1998 mosel vitelic V53C8125H dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0 v, unless otherwise specified. symbol parameter access time V53C8125H unit test conditions notes min. typ. max. i li input leakage current (any input pin) 10 10 m av ss v in v cc i lo output leakage current (for high-z state) 10 10 m av ss v out v cc ras , cas at v ih i cc1 v cc supply current, operating 30 180 ma t rc = t rc (min.) 1, 2 35 160 40 150 45 145 50 135 i cc2 v cc supply current, ttl standby 4 ma ras , cas at v ih , other inputs 3 v ss i cc3 v cc supply current, ras -only refresh 30 180 ma t rc = t rc (min.) 2 35 160 40 150 45 145 50 135 i cc4 v cc supply current, fast page mode operation 30 110 ma minimum cycle 1, 2 35 95 40 90 45 85 50 80 i cc5 v cc supply current, standby output enable other inputs 3 v ss 2 ma ras = v ih cas = v il 1 i cc6 v cc supply current, cmos standby 1 ma ras 3 v cc 0.2 v, cas 3 v cc 0.2 v, all other inputs 3 v ss v cc supply voltage 4.5 5.5 v v il input low voltage 1 0.8 v 3 v ih input high voltage 2.4 v cc + 1 v 3 v ol output low voltage 0.4 v i ol = 4.2 ma v oh output high voltage 2.4 2.4 v i oh = 5 ma
mosel vitelic V53C8125H 5 V53C8125H re v . 1.7 august 1998 ac characteristics t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0v unless otherwise noted ac test conditions, input pulse levels 0 to 3v # symbol parameter 30 35 40 45 50 unit notes min. max. min. max. min. max. min. max. min. max. 1t ras ras pulse width 30 75k 35 75k 40 75k 45 75k 50 75k ns 2t rc read or write cycle time 65 70 75 80 90 ns 3t rp ras precharge time 25 25 25 25 30 ns 4t csh cas hold time 30 35 40 45 50 ns 5t cas cas pulse width 56789 n s 6t rcd ras to cas delay 15 20 16 24 17 28 18 32 19 36 ns 7t rcs read command setup time 00000 n s 4 8t asr row address setup time 00000 n s 9t rah row address hold time 56789 n s 10 t asc column address setup time 00000 n s 11 t cah column address hold time 55567 n s 12 t rsh (r) ras hold time (read cycle) 10 10 10 10 10 ns 13 t crp cas to ras precharge time 55555 n s 14 t rch read command hold time referenced to cas 00 000 n s 5 15 t rrh read command hold time referenced to ras 0 0000 n s 5 16 t roh ras hold time referenced to oe 6789 1 0 n s 17 t oac access time from oe 10 11 12 13 14 ns 12 18 t cac access time from cas 10 11 12 13 14 ns 6,7,14 19 t rac access time from ras 30 35 40 45 50 ns 6, 8, 9 20 t caa access time from column address 16 18 20 22 24 ns 6,7,10 21 t lz oe or cas to low-z output 00000 n s 1 6 22 t hz oe or cas to high-z output 0506060708 n s 1 6 23 t ar column address hold time from ras 26 28 30 35 40 ns 24 t rad ras to column address delay time 10 14 11 17 12 20 13 23 14 26 ns 11 25 t rsh (w) ras or cas hold time in write cycle 10 10 10 10 10 ns 26 t cwl write command to cas lead time 10 11 12 13 14 ns 27 t wcs write command setup time 00000 n s 12, 13 28 t wch write command hold time 55567 n s
6 V53C8125H re v . 1.7 august 1998 mosel vitelic V53C8125H 29 t wp write pulse width 55567 n s 30 t wcr write command hold time from ras 26 28 30 35 40 ns 31 t rwl write command to ras lead time 10 11 12 13 14 ns 32 t ds data in setup time 00000 n s 1 4 33 t dh data in hold time 55567 n s 1 4 34 t woh write to oe hold time 55678 n s 1 4 35 t oed oe to data delay time 55678 n s 1 4 36 t rwc read-modify-write cycle time 100 105 110 115 130 ns 37 t rrw read-modify-write cycle ras pulse width 65 70 75 80 87 ns 38 t cwd cas to we delay 26 28 30 32 34 ns 12 39 t rwd ras to we delay in read- modify-write cycle 50 54 58 62 68 ns 12 40 t crw cas pulse width (rmw) 44 46 48 50 52 ns 41 t awd col. address to we delay 32 35 38 41 42 ns 12 42 t pc fast page mode read or write cycle time 19 21 23 25 28 ns 43 t cp cas precharge time 44567 n s 44 t car column address to ras setup time 16 18 20 22 24 ns 45 t cap access time from column precharge 19 21 23 25 27 ns 7 46 t dhr data in hold time referenced to ras 26 28 30 35 40 ns 47 t csr cas setup time cas - before- ras refresh 10 10 10 10 10 ns 48 t rpc ras to cas precharge time 00000 n s 49 t chr cas hold time cas -before- ras refresh 7 8 8 10 12 ns 50 t pcm fast page mode read-modify- write cycle time 56 58 60 65 70 ns 51 t t transition time (rise and fall) 3 50 3 50 3 50 3 50 3 50 ns 15 52 t ref refresh interval (512 cycles) 88888 m s 1 7 # symbol parameter 30 35 40 45 50 unit notes min. max. min. max. min. max. min. max. min. max. ac characteristics (cont d)
7 mosel vitelic V53C8125H V53C8125H re v . 1.7 august 1998 notes: 1. i cc is dependent on output loading when the device output is se lected. specified i cc (max.) is measured with the output open. 2. i cc is dependent upon the number of address transitions. speci fied i cc (max.) is measured with a maximum of two transitions per address cycle in fast page mode. 3. specified v il (min.) is steady state operating. during transitions, v il (min.) may undershoot to 1.0 v for a period not to exceed 20 ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v cc . 4. t rcd (max.) is specified for reference only. operation within t rcd (max.) limits insures that t rac (max.) and t caa (max.) can be met. if t rcd is greater than the specified t rcd (max.), the access time is controlled by t caa and t cac . 5. either t rrh or t rch must be satisified for a read cycle to occur. 6. measured with a load equivalent to two ttl inputs and 50 pf. 7. access time is determined by the longest of t caa , t cac and t cap . 8. assumes that t rad t rad (max.). if t rad is greater than t rad (max.), t rac will increase by the amount that t rad exceeds t rad (max.). 9. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), t rac will increase by the amount that t rcd exceeds t rcd (max.). 10. assumes that t rad 3 t rad (max.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t caa and t cac . 12. t wcs , t rwd , t awd and t cwd are not restrictive operating parameters. 13. t wcs (min.) must be satisfied in an early write cycle. 14. t ds and t dh are referenced to the latter occurrence of cas or we . 15. t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 3 ns. 16. assumes a three-state test load (5 pf and a 380 ohm thevenin equivalent). 17. an initial 200 m s pause and 8 ras -containing cycles are required when exiting an extended per iod of bias without clocks. an extended period of time without clocks is defined as one that exceeds the specified refresh interval.
8 mosel vitelic V53C8125H V53C8125H re v . 1.7 august 1998 waveforms of read cycle waveforms of early write cycle ih v il v ras ih v il v cas ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (r)(12) t cas (5) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rad (24) t rah (9) t asr (8) t rcs (7) t rch (14) t rrh (15) t car (44) t caa (20) t cac (18) t t hz (22) t lz (21) ih v il v we oh v ol v i/o 8125h 04 v alid da t a-out address rac (19) column address row address t oac (17) t hz (22) ih v il v oe t roh (16) ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (w)(25) t cas (5) t rcd (6) t crp (13) t cah (1 1) t t rad (24) t rah (9) t asr (8) t t wcr (30) t r wl (31) t dh (33) t dhr (46) ih v il v ih v il v ih v il v 8125h 05 t t cwl (26) wch (28) t t ds (32) column address v alid da t a-in high-z ras cas we oe i/o address t car (44) asc (10) wcs (27) wp (29) row address don ? t care undefined
9 mosel vitelic V53C8125H V53C8125H re v . 1.7 august 1998 waveforms of oe -controlled write cycle waveforms of read-modify-write cycle ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rah (9) t asr (8) row address column address t woh (34) t dh (33) t oed (35) ih v il v ih v il v ih v il v 8125h 06 v alid da t a-in t ds (32) t rad (24) ras cas we oe i/o t csh (4) address t car (44) t t cas (5) rsh (w)(12) t wp (29) r wl (31) t cwl (26) t column address row address v v ih v il v ih v il v t rp (3) t crp (13) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rah (9) t asr (8) wp (29) r wl (31) t oed (35) t ih v il v ih v il v ih v il v 8125h 07 v alid da t a-out t rac (19) t cwl (26) t t rad (24) t t oac (17) t t dh (33) t ds (32) hz (22) cac (18) t lz (21) v alid da t a-in ih v il v oh ol ras cas we oe i/o address t r wc (36) t rr w (37) t ar (23) t csh (4) t rsh (w)(25) t cr w (40) t r wd (39) cwd (38) t a wd (41) t t caa (20) don ? t care undefined
10 mosel vitelic V53C8125H V53C8125H re v . 1.7 august 1998 waveforms of fast page mode read cycle waveforms of fast page mode write cycle v alid da t a out v alid da t a out column address cac (18) t t hz (22) hz (22) hz (22) hz (22) row address column address ih v il v ih v il v rp (3) t ih v il v ih v il v oh v ol v t rah (9) t asr (8) t rcs (7) t rch (14) t csh (4) 8125h 08 ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (r)(12) t cas (5) t cah (1 1) t hz (22) t t ar (23) t cas (5) t cas (5) pc (42) t crp (13) t t column address t t car (44) t cah (1 1) t rcs (7) t rcs (7) t rch (14) t oac (17) t t t oac (17) t caa (20) t rrh (15) t hz (22) lz (21) t rac (19) t t cac (18) v alid da t a out t crp (13) t t lz (21) t ras cas we oe i/o address t asc (10) t lz (21) cac (18) t caa (20) oac (17) cap (45) t cah (1 1) row add ih v il v ih v il v ih v il v ih v il v t t asr (8) 8125h 09 ih v il v cp (43) t asc (10) rcd (6) t rsh (w)(25) column address t cah (1 1) t cas (5) t cas (5) t car (44) t rad (24) t cwl (26) v alid da t a in t crp (13) t wcs (27) wp (29) t cah (1 1) t asc (10) t cah (1 1) t dh (33) t ds (32) ih v il v column address rah (9) column address t crp (13) t t wch (28) t cwl (26) t wcs (27) wp (29) t wch (28) t t cwl (26) t wcs (27) wp (29) t wch (28) t v alid da t a in t dh (33) t ds (32) v alid da t a in t dh (33) t ds (32) t rp (3) t ar (23) ras cas we oe i/o address open open t r wl (31) t t csh (4) t ras (1) t pc (42) t t cas (5) don ? t care undefined
11 mosel vitelic V53C8125H V53C8125H re v . 1.7 august 1998 waveforms of fast page mode read-write cycle waveforms of ras -only refresh cycle row add ih v il v ih v il v rp (3) t ih v il v i/oh v i/ol v t t asr (8) column address 8125h 10 ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (w)(25) column address t cah (1 1) t cas (5) t cas (5) t t t crp (13) t rcs (7) t cah (1 1) t asc (10) t t cwd (38) t lz (21) ih v il v column address t asc (10) rah (9) t wp (29) t cwl (26) t t cwl (26) t r wl (31) t a wd (41) t caa (20) t t oac (17) t a wd (41) t oac (17) in t cac (18) t oed (35) t ds (32) t dh (33) t lz (21) in out hz (22) t oed (35) ds (32) t dh (33) t t t t cac (18) t caa (20) lz (21) in hz (22) t oed (35) ds (32) t dh (33) t t t cac (18) t caa (20) t t wp (29) t t wp (29) t cwl (26) t car (44) t rad (24) ras cas we oe i/o address t a wd (41) out rac (19) t oac (17) t r wd (39) cah (1 1) pcm (50) t t csh (4) t cas (5) t cwd (38) hz (22) cwd (38) out cap (45) cap (45) ih v il v ras ih v il v rp (3) t ih v il v cas t ras (1) t rc (2) t crp (13) t asr (8) t rah (9) 8125h 11 we, oe = don ? t care note: address row addr don ? t care undefined
12 mosel vitelic V53C8125H V53C8125H re v . 1.7 august 1998 waveforms of cas -before-ras refresh counter test cycle waveforms of cas -before-ras refresh cycle ih v il v ih v il v rp (3) t ih v il v t csr (47) t rsh (w)(25) 8125h 12 t ras (1) t chr (49) t rcs (7) t wcs (27) t lz (21) ih v il v ih v il v ih v il v t dh (33) t cp (43) t cas (5) t rch (14) t rrh (15) t roh (16) t oac (17) t hz (22) t hz (22) t r wl (31) t cwl (26) t ds (32) ih v il v ih v il v ih v il v read cycle write cycle t wch (28) i/o address we we i/o d out d in ras cas oe oe i/o ih v il v ras oh v ol v ih v il v cas t ras (1) t rc (2) t cp (43) t hz (22) t csr (47) 8125h 13 rp (3) t t rpc (48) t chr (49) rp (3) t we, oe, = don ? t care note: a ? a 0 7 don ? t care undefined
13 mosel vitelic V53C8125H V53C8125H re v . 1.7 august 1998 waveforms of hidden refresh cycle (read) waveforms of hidden refresh cycle (write) ih v il v oh v ol v rp (3) t ih v il v t asr (8) t crp (13) t rcd (6) t rsh (r)(12) t rcs (7) 8125h 14 t chr (49) t rad (24) t asc (10) t t cah (1 1) row add column address t rrh (15) t oac (17) t lz (21) t hz (22) t hz (22) ih v il v ih v il v ih v il v ras cas we oe i/o address v alid da t a rah (9) t caa (20) t cac (18) t rac (19) t ras (1) rp (3) t t ras (1) t ar (23) t crp (13) t rc (2) t rc (2) ih v il v ih v il v rp (3) t ih v il v t ras (1) t rc (2) t asr (8) t crp (13) rp (3) t t rcd (6) t rsh (12) t wcs (27) 8125h 15 t ras (1) t ar (23) t chr (49) t crp (13) t rad (24) t asc (10) t rah (9) t cah (1 1) row add column address t wch (28) t ds (32) ih v il v ih v il v ih v il v v alid da t a-in t dhr (46) t rc (2) ras cas we oe i/o address t dh (33) don ? t care undefined
14 mosel vitelic V53C8125H V53C8125H re v . 1.7 august 1998 functional description the V53C8125H is a cmos dynamic ram opti- mized for high data bandwidth, low power applica- tions. it is functionally similar to a traditional dynamic ram. the V53C8125H reads and writes data by multiplexing an 17-bit address into a 8-bit row and an 9-bit column address. the row address is latched by the row address strobe (ras ). the column address ? flows through ? an internal address buffer and is latched by the column address strobe (cas ). because access time is primarily dependent on a valid column address rather than the precise time that the cas edge occurs, the delay time from ras to cas has little effect on the access time. memory cycle a memory cycle is initiated by bringing ras low. any memory cycle, once initiated, must not be end- ed or aborted before the minimum t ras time has ex- pired. this ensures proper device operation and data integrity. a new cycle must not be initiated until the minimum precharge time t rp /t cp has elapsed. read cycle a read cycle is performed by holding the write enable (we ) signal high during a ras /cas opera- tion. the column address must be held for a mini- mum specified by t ar . data out becomes valid only when t oac , t rac , t caa and t cac are all satisifed. as a result, the access time is dependent on the timing relationships between these parameters. for exam- ple, the access time is limited by t caa when t rac , t cac and t oac are all satisfied. write cycle a write cycle is performed by taking we and cas low during a ras operation. the column ad- dress is latched by cas . the write cycle can be we controlled or cas controlled depending on whether we or cas falls later. consequently, the input data must be valid at or before the falling edge of we or cas , whichever occurs last. in the cas - controlled write cycle, when the leading edge of we occurs prior to the cas low transition, the i/o data pins will be in the high-z state at the beginning of the write function. ending the write with ras or cas will maintain the output in the high-z state. in the we controlled write cycle, oe must be in the high state and t oed must be satisfied. refresh cycle to retain data, 256 refresh cycles are required in each 8 ms period. there are two ways to refresh the memory: 1. by clocking each of the 512 row addresses (a 0 through a 8 ) with ras at least once every 8 ms. any read, write, read-modify-write or ras - only cycle refreshes the addressed row. 2. using a cas -before-ras refresh cycle. if cas makes a transition from low to high to low after the previous cycle and before ras falls, cas -before-ras refresh is activated. the V53C8125H uses the output of an internal 9-bit counter as the source of row addresses and ig- nore external address inputs. cas -before-ras is a ? refresh-only ? mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cy- cle. a cas -before-ras counter test mode is provid- ed to ensure reliable operation of the internal refresh counter. fast page mode operation fast page mode operation permits all 256 col- umns within a selected row of the device to be ran- domly accessed at a high data rate. maintaining ras low while performing successive cas cycles retains the row address internally and eliminates the need to reapply it for each cycle. the column ad- dress buffer acts as a transparent or flow-through latch while cas is high. thus, access begins from the occurrence of a valid column address rather than from the falling edge of cas , eliminating t asc and t t from the critical timing path. cas latches the address into the column address buffer and acts as an output enable. during fast page mode opera- tion, read, write, read-modify-write or read- write-read cycles are possible at random address- es within a row. following the initial entry cycle into fast page mode, access is t caa or t cap controlled. if the column address is valid prior to the rising edge of cas , the access time is referenced to the cas rising edge and is specified by t cap . if the column address is valid after the rising cas edge, access is timed from the occurrence of a valid address and is specified by t caa . in both cases, the falling edge of cas latches the address and enables the output.
mosel vitelic V53C8125H 15 V53C8125H re v . 1.7 august 1998 fast page mode provides sustained data rates up to 53 mhz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. the following equation can be used to calculate the maximum data rate: data output operation the V53C8125H input/output is controlled by oe , cas , we and ras . a ras low transition en- ables the transfer of data to and from the selected row address in the memory array. a ras high tran- sition disables data transfer and latches the output data if the output is enabled. after a memory cycle is initiated with a ras low transition, a cas low transition or cas low level enables the internal i/o path. a cas high transition or a cas high level dis- ables the i/o path and the output driver if it is en- abled. a cas low transition while ras is high has no effect on the i/o data path or on the output driv- ers. the output drivers, when otherwise enabled, can be disabled by holding oe high. the oe signal has no effect on any data stored in the output latch- es. a we low level can also disable the output driv- ers when cas is low. during a write cycle, if we goes low at a time in relationship to cas that would normally cause the outputs to be active, it is neces- sary to use oe to disable the output drivers prior to the we low transition to allow data in setup time (t ds ) to be satisfied. power-on after application of the v cc supply, an initial pause of 200 m s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a ras clock). eight initialization cycles are required after extended periods of bias without clocks (greater than the refresh interval). during power-on, the v cc current requirement of the V53C8125H is dependent on the input levels of ras and cas . if ras is low during power-on, the device will go into an active cycle and i dd will exhibit current transients. it is recommended that ras and cas track with v cc or be held at a valid v ih during power-on to avoid current surges. table 1. V53C8125H data output operation for various cycle types data rate 256 t rc 255 t pc + --------------------------------------- - = cycle type i/o state read cycles data from addressed memory cell cas -controlled write cycle (early write) high-z we -controlled write cycle (late write) oe controlled. high oe = high-z i/os read-modify-write cycles data from addressed memory cell fast page mode read data from addressed memory cell fast page mode write cycle (early write) high-z fast page mode read-modify- write cycle data from addressed memory cell ras -only refresh high-z cas -before-ras refresh cycle data remains as in previous cycle cas -only cycles high-z
16 mosel vitelic V53C8125H V53C8125H re v . 1.7 august 1998 package diagrams 26/24-pin 300 mil soj 28-pin tsop-i 0.05 t yp . [1.27 t yp .] 0.018 t yp . [0.457 t yp .] 0.665 ? 0.698 [16.89 ? 17.73] 0.025 min. [0.635 min.] 0.125 ? 0.135 [3.175 ? 3.429] 0.028 t yp . [0.711 t yp .] 0.332 ? 0.342 [8.43 ? 8.69] unit in inches [mm] 0.296 ? 0.304 [7.52 ? 7.72] 0.255 ? 0.275 [6.477 ? 6.985] 0.082 ? 0.093 [2.08 ? 2.36] detail ? a ? .520 ? .535 .035 ? .043 .035 ? .043 .311 ? .319 unit in inches .037 ? .041 .020 ? .028 0 ? 6 .004 ? .008 d d .007 ? .009 .007 ? .011 .004 ? .006 base metal with plating .08 ? .20 .055 ? .063 .055 ? .063 c.o.o. denotes country of orgin .012 max 0.25 bsc gage plane .022 .039 dia. pin # 1 i.d. see detail ? a ? top view bottom view see detail ? b ? detail ? b ? detail ? a ? section ? d-d ? .047 .002 ? .006 .000 .004 .079 dia. x deep fixed pin (1 plcs.) .022 .004 .022 .010 .461 ? .469
mosel vitelic w orld wide offices V53C8125H cop yr ight 1998, mosel vitelic inc. 7/98 pr inted in u .s .a. mosel vitelic 3910 n. first street, san jose , ca 95134-1501 ph: (408) 433-6000 f ax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change withou t notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality contro l sampling techniques which are intended to provide an assuran ce of high quality products suitable for usual commercial appli ca- tions. mosel vitelic does not do testing appropriate to prov ide 100% product quality assurance and does not assume any liabi l- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in whi ch personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applicatio ns. u .s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2665-4883 fax: 852-2664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-578-3344 fax: 886-3-579-2838 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 81-43-299-6000 fax: 81-43-299-6555 ireland & uk block a unit 2 broomfield business park malahide co. dublin, ireland phone: +353 1 8038020 fax: +353 1 8038049 germany (continental europe & israel ) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341

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